This invention claims the benefit of provisional application No. 60/323,188, filed Sep. 17, 2001, which is hereby incorporated by reference herein in its entirety.
A programmable logic device (xe2x80x9cPLDxe2x80x9d) is typically designed to be usable in any of a wide range of possible applications. This allows the PLD to be manufactured in large quantities and sold to a large number of customers, each of whom may program it differently for a different use. Large volume production helps to reduce the unit cost of the PLD. Up to a point at least, the more possible uses the PLD can satisfy, the more customers will buy it for their individual needs and the larger the volume of production of the PLD can be, thereby lowering its unit cost further and further. Of course, too general a PLD may become excessively large and complex, thereby exerting cost-increasing pressure on the economics of the device. It is therefore necessary to strike a balance between too little and too much functionality in a PLD. The present invention relates to providing increased but not excessively increased functionality in a PLD.
PLDs are increasingly of interest for use in providing or at least supporting high speed communication. Among the communication protocols that it may be desirable to use PLDs with are several 8-bit/10-bit (xe2x80x9c8B10Bxe2x80x9d) protocols such as those known as XAUI, InfiniBand, Gigabit Ethernet, and the like, and non-8B10B protocols such as Packet Over Sonet or POS-5 and the like. These various protocols are industry standards, and so they do not need to be described in full detail here. They will already be familiar to those skilled in the art, or they can be learned from the publications of the industry groups that sponsor and maintain them. (Although these industry-standard protocols serve as a point of reference for this invention, the invention is not limited to these standards and can also implement many non-standard variations of these protocols.)
Although all the protocols mentioned above are different from one another in at least some respects, all of the 8B10B protocols have some general characteristics in common with one another that are quite different from the non-8B10B protocols (hereinafter generally referred to for convenience as POS-5 protocols; although, again, more than true industry-standard POS-5 is included in the term xe2x80x9cPOS-5xe2x80x9d as used herein). For example, the 8B10B protocols tend to make use of relatively small numbers of serial data channels in parallel (e.g., up to four data channels), but allow relatively large amounts of skew (relative signal transmission delay) among those channels. At least some of the 8B10B protocols may allow skew of as much as several byte transmission times among the various channels. The POS-5 protocols, on the other hand, tend to make use of larger numbers of serial data channels in parallel (e.g., up to 16 data channels), but allow only relatively small amounts of skew among those channels. For example, POS-5 protocols may only allow skew of up to three high-speed clock intervals (i.e., three serial data bit intervals) among the channels.
Other related differences of a fundamental nature between 8B10B and POS-5 protocols include the provision in POS-5 of a separate de-skew reference channel and a separate reference clock signal channel, neither of which are part of 8B10B protocols, at least in their industry-standard forms.
These relatively fundamental differences in characteristics between 8B10B and POS-5 protocols make it difficult to envision circuitry that can support them both, especially with respect to such functions as byte synchronization and channel alignment. Byte synchronization relates to finding the boundaries between successive bytes in incoming serial bit streams. Channel alignment relates to determining the amount of, and then eliminating or at least compensating for, skew among the incoming data channels. For example, the amount of skew allowed in POS-5 protocols is so small that it can generally be taken care of as part of byte synchronization. That tends not to be true for 8B10B protocols, which typically require separate channel alignment circuitry in addition to byte synchronization circuitry.
On the other hand, it would not be as economical or efficient on a PLD to provide completely or largely separate circuitry for interfacing with each of these two classes of protocols.
In accordance with this invention a PLD has programmable logic circuitry and communication interface circuitry for supporting both 8B10B and POS-5 communication protocols. The interface circuitry facilitates use of the programmable logic circuitry to receive or transmit information via either 8B10B or POS-5 protocols. The interface circuitry includes a number of elements that are hard-wired to at least a large extent to perform various tasks required in the interface. Although these components are largely hard-wired to help speed them up, at least some of them are also partly programmable to enable them to operate differently in some respects to support different communication protocols. Among the components provided in the interface are byte synchronization circuitry and channel alignment circuitry. These elements are included in the circuitry where (if required) they can support both 8B10B and POS-5 protocols. The interface circuitry may include programmable signal routing for such purposes as effectively changing the location in the circuit of the byte synchronization circuitry and/or allowing the channel alignment circuitry to be either included in or excluded from the circuitry as required.
To facilitate supporting both 8B10B and POS-5 protocols, a PLD in accordance with this invention includes programmable logic circuitry and multiple channels of communication circuitry. At least some of the communication channels can be used as main data channels for receiving respective streams of serial data bits representing successive bytes of information as in either 8B10B or POS-5 communication. At least one of the communication channels is optionally usable to receive a further stream of serial data bits successively representing samples of the bytes approximately concurrently passing through the main data channels one after another, as in POS-5 communication. Each main data channel includes byte synchronization circuitry that is programmable to identify bytes in the associated data stream based on analysis of that stream (as in 8B10B communication), and that is alternatively programmable to identify bytes in the associated data stream based on byte identification performed in and by the reference data channel (as in POS-5 communication).
Another feature that a PLD may have in accordance with this invention is clock data recovery (xe2x80x9cCDRxe2x80x9d) circuitry in the above-mentioned communication channels, phase locked loop (xe2x80x9cPLLxe2x80x9d) circuitry for providing a reference clock signal for use by the CDR circuitry, and selection circuitry adapted to select a clock signal for use by the PLL circuitry from either a reference clock signal from the external source of the data applied to the communication channel (as in POS-5 communication), or from a source other than the external source (e.g., an oscillator more locally associated with the PLD, as in 8B10B communication).
Still another feature that a PLD may have in accordance with this invention is channel alignment circuitry in each of the above-mentioned main data channels. The channel alignment circuitry in each main channel is programmable to synchronize the data in that channel with data in other main channels based on comparison of data between the main data channels (as in 8B10B communication). Alternatively, the channel alignment circuitry in each main channel is programmable to synchronize the data in that channel with data in other main channels based on comparison of data between the main and reference data channels (as in POS-5 communication). In the latter case, the channel alignment may actually be performed by what is elsewhere referred to as byte synchronization circuitry in the main data channels.